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. TSMC 2024 ฟอรั่มเทคโนโลยีอเมริกาเหนือ

TSMC, ผู้นำระดับโลกในผ้าเซมิคอนดักเตอร์, showcased its latest advancements at the 2024 North American Technology Forum. This event highlights TSMC"s continuous innovation and leadership in the semiconductor industry.Driven by the explosive growth of AI, which demands more computing power, higher bandwidth, and larger-scale heterogeneous integration, TSMC has responded to the escalating needs of NVIDIA and other clients by advancing its chip manufacturing process from N16 (16nm) to N3 (3nm) and is poised to launch N16 (1.6nm) by 2026. The number of transistors in AI GPUs has reached an astonishing 200 billion and above.With Nvidia and other clients pushing the envelope for AI and HPC computing power and bandwidth, TSMC has significantly increased its investment in research and development, boasting over 9,000 R&D personnel and a budget of $5.846 billion. This has resulted in a comprehensive roadmap of TSMC"s advanced technologies:For high-end products, including advanced mobile devices, data centers, servers, AI accelerators, gaming, and ADAS, TSMC is currently utilizing N3E and N5A processes, with plans to introduce the N16 process in 2026.Mainstream products, such as mid-range to low-end mobile devices and clients" base stations and networks, are currently being manufactured with N4P technology, which will be upgraded to N3P by 2026.TSMC"s NanoFlex innovation has maximized the number of nanosheet elements while maintaining optimal performance, power, and area balance through flexible element width modulation. This optimization has enabled the creation of elements with lower heights that reduce area and power consumption, while higher elements boost performance by

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up to 15%. These elements coexist within a single module.The upcoming A16 (1.6nm) process introduces a novel power supply mechanism known as SPR (Super Power Rail), which separates the power lines from the signal lines. This approach enhances logic density and performance, while reducing power transmission and minimizing voltage drops. The new backside contacts maintain the density of gates and flexibility in element modulation.Compared to the N2P (2nm) process, the A16 chip offers an 8-10% increase in performance at the same voltage, and a 15-20% reduction in power consumption for the same performance, with a 1.1x increase in chip density.For cost-effective N4C (4nm) technology, TSMC provides an 8.5% reduction in die cost, alongside a simple implementation. This technology is an extension of N4P, compatible with it, and strikes a good balance between cost and design complexity.TSMC"s new approach to AI integration includes a high-performance computing platform that combines traditional CoWoS (chip on wafer on substrate) with a silicon photonics module for direct interconnection with the substrate and other chips. This technology is speculated to be part of the company"s CPO (chip-on-package) initiative, offering a solution to the high power consumption of traditional สลับชิป - โมดูลออปติคอล serdes. While the LPO (lightweight photonic module) approach may suffice for 112G serdes, challenges arise with 224G and beyond, necessitating alternative solutions. The CPO method aims to address these issues by integrating the photonics module with the exchange chip on the same substrate, significantly reducing serdes power consumption. The client receives a chip that is directly interfaced with a light source on the CPO module,

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